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Makefile: use $(CC) more consistently. 

Explicitly calling 'gcc' in some rules makes it hard to test with
other compilers.
This commit is contained in:
NeilBrown 2009-04-29 11:21:08 +10:00
parent 25affb56b9
commit 667e66d329
1 changed files with 3 additions and 3 deletions
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6
Makefile
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@ -111,13 +111,13 @@ mdadm.tcc : $(SRCS) mdadm.h
mdadm.klibc : $(SRCS) mdadm.h
rm -f $(OBJS)
gcc -nostdinc -iwithprefix include -I$(KLIBC)/klibc/include -I$(KLIBC)/linux/include -I$(KLIBC)/klibc/arch/i386/include -I$(KLIBC)/klibc/include/bits32 $(CFLAGS) $(SRCS)
$(CC) -nostdinc -iwithprefix include -I$(KLIBC)/klibc/include -I$(KLIBC)/linux/include -I$(KLIBC)/klibc/arch/i386/include -I$(KLIBC)/klibc/include/bits32 $(CFLAGS) $(SRCS)
mdadm.Os : $(SRCS) mdadm.h
gcc -o mdadm.Os $(CFLAGS) -DHAVE_STDINT_H -Os $(SRCS)
$(CC) -o mdadm.Os $(CFLAGS) -DHAVE_STDINT_H -Os $(SRCS)
mdadm.O2 : $(SRCS) mdadm.h
gcc -o mdadm.O2 $(CFLAGS) -DHAVE_STDINT_H -O2 $(SRCS)
$(CC) -o mdadm.O2 $(CFLAGS) -DHAVE_STDINT_H -O2 $(SRCS)
test_stripe : restripe.c mdadm.h
$(CC) $(CXFLAGS) $(LDFLAGS) -o test_stripe -DMAIN restripe.c